An SR latch circuit (Set/Reset) is an asynchronous device: it works independently of control signals and relies only on the state of the S and R inputs. When a high is applied to the Set line of an SR latch, the Q output goes high. The SR latch circuit has a feedback mechanism that causes the Q output to remain high, even when the S input goes low again. This is how the latch circuit serves as a memory device. Conversely, a high input on the Reset line will drive the Q output low, effectively resetting the latch's “memory”. When both inputs are low, the latch circuit “latches”—it remains in its previously set or reset state.